Alternate booth partial product generation for a hardware multiplier

ABSTRACT

In hardware multipliers, the generation of partial products is a necessary step in the process known to the art for efficient production of a final product. A way to increase the speed of hardware multipliers is through the use of the Booth algorithm. The alternate Booth partial product generation for hardware multipliers of the present invention is directed to a method and apparatus for eliminating the encoding of the bits of the multiplier prior to entering the partial product generating cell of the present invention which may result in less hardware and increased speed.

FIELD OF THE INVENTION

The present invention relates generally to hardware multipliers, andmore specifically to an apparatus and method for producing partialproducts which may be utilized in hardware multiplication.

BACKGROUND OF THE INVENTION

Many of the processes performed by information handling systems and thelike involve the multiplication of binary numbers. In a multiplicationfunction, there exists a multiplicand and a multiplier. Well known tothe art, binary numbers are multiplied through a process of multiplyingthe multiplicand by the first bit of the multiplier. Next, themultiplicand is multiplied by the second bit of the multiplier, shiftingthe result one digit and adding the products. This process is continueduntil each bit of the multiplier has been multiplied by themultiplicand.

Each of the products produced by multiplying the multiplicand by a bitof the multiplier produces a number which is referred to as a partialproduct. The resulting product is formed by accumulating the partialproducts propagating the carries from the rightmost columns to the left.This process is referred to as partial product accumulation. Althoughthis process works well for its intended purpose, it has a significantdrawback in that in order to implement this process utilizing hardware,a significant number of items of hardware are required. As a result,implementing this process with hardware may be cost prohibitive and maybe slow especially for large bit numbers.

In order to speed up the process, the Booth algorithm has been utilized.This algorithm allows for a reduction of the number of partial productsusing a redundant number system. When this process is implemented inhardware, the bits of the multiplier must be separately recoded in orderto produce the partial products. Unfortunately, this requires anadditional step which slows the process.

Consequently, it would be advantageous to provide an apparatus andmethod for generating partial products which did not require theadditional step of recoding the multiplier bits. By eliminating therecoding of the multiplier bits, the process time is reduced.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a novel apparatus forthe generation of partial products for a hardware multiplier. Thepartial product generator of the present invention does not requirerecoding of the bits of the multiplier prior to entering the partialproduct generator of the present invention in order to generate thepartial products. The present invention is further directed to a methodof producing partial products for a hardware multiplier by directlysending the multiplier bits to the partial product generator of thepresent invention.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory onlyand are not restrictive of the invention claimed. The accompanyingdrawings, which are incorporated in and constitute a part of thespecification, illustrate an embodiment of the invention and togetherwith the general description, serve to explain the principles of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

The numerous objects and advantages of the present invention may bebetter understood by those skilled in the art by reference to theaccompanying figures in which:

FIG. 1 is a block diagram representing a partial product generator wellknown to the art;

FIG. 2 is a block diagram representing an exemplary embodiment of thepresent invention;

FIG. 3 depicts an exemplary partial product generator cell of thepresent invention;

FIG. 4 is a schematic diagram of an exemplary partial product generatorcell of the present invention;

FIG. 5 is a truth table representing exemplary combinations ofmultiplier bits and the partial product which may be produced by eachcombination of multiplier bits; and

FIG. 6 is a flow diagram representing the stages of the multiplicationprocess.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the presently preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings.

Referring now to FIG. 1, a partial product generator well known to theart is shown in block diagram form. Through the use of the Boothalgorithm, it is desirable to calculate partial products and manipulatethe partial products in order to obtain the final product of amultiplication function. In the multiplication of a set of multiplicandinput bits and a set of multiplier input bits, the set of multiplierinput bits must enter a Booth encoder. This is a necessary step becausepartial product generators known to the art are unable to calculatepartial products without recoding the set of multiplier input bits.After recoding of the set of multiplier input bits, the recoded set ofbits are connected to the partial product generator well known in theart. Upon the entering of the recoded set of bits to the partial productgenerator, the partial product is produced by selecting the propermultiple of the multiplicand.

A block diagram of the partial product generator of the presentinvention is shown in FIG. 2. The partial product generator of thepresent invention does not require that the set of multiplier bits berecoded prior to entering the partial product generator. As a result, astep in the process of hardware multiplication known to the art has beeneliminated. This allows for faster generation of partial products whichin turn allows for faster generation of a final product in amultiplication problem.

A new and improved apparatus and method for generating a partial productas described in the present invention is shown in an exemplary fashionin a block diagram in FIG. 3. In an exemplary embodiment, the partialproduct generator cell of the present invention is capable of producinga bit j of the i-th partial product without recoding the set ofmultiplier input bits prior to entering the cell. FIG. 3 illustrates athree multiplier bit input and two multiplicand bit input embodimentwhich may be required for a radix 4 partial product. The multiplier bitinputs are represented by m[i], m[i+1], and m[i+2], and the multiplicandbit inputs are represented by M[J] and M[−1]. In an exemplaryembodiment, the partial product generator cell generates bit j of thei-th partial product.

The exemplary embodiment of the partial product generator cell of thepresent invention illustrated in a block diagram in FIG. 3 isillustrated in exemplary fashion in the schematic of FIG. 4. The cellcomprises three multiplexors, each multiplexor includes two data inputs,a control input, and an output. The cell further comprises an AND gate,a NAND gate, five inverters and a two input two stack AOI gate. Eachcell may calculate bit j of the i-th partial product for everycombination of a set of three multiplier bits m[i], m[i+1], and m[i+2]and a set of two multiplicand bits M[j] and M[j−1].

A second data input of the first multiplexor 410 is connected to theoutput lead of an inverter 470 whose input lead is connected to amultiplier bit m[i] 401. The first data input of the first multiplexor410 is connected to a multiplicand bit m[i] 401 directly. The controlinput of the first multiplexor 410 is connected to the multiplier bitm[i+1] 402. The output of the first multiplexor 410 is connected to theinput of a second inverter 472 whose output is connected to a secondinput of the two input two stack AOI gate.

The first data input of the second multiplexor 420 is connected to themultiplicand bit M[j] 412. The second data input of the secondmultiplexor 420 is connected to the multiplicand bit M[j−1] 411. Thecontrol input of the second multiplexor 420 is connected to the outputlead of a second inverter 472. The output of the second multiplexor 420is connected to the input lead of a fourth inverter 476 whose outputlead is connected to the second input of a NAND gate 450.

An AND gate 440 is another element of the cell whose inputs are thefirst multiplier bit 401 and the multiplier bit m[i+1] 402. The outputof the AND gate 440 is connected to the first of the two input two stackAOI gate 460. The second and fourth inputs of the two input two stackAOI gate 460 are connected to the multiplicand bit M[j−1] 411 and themultiplicand bit M[j] 412 respectively. The output of the two input twostack AOI gate 460 is connected to a second data input of a thirdmultiplexor 430. The output of the AND gate 440 is also connected to theinput lead of a third inverter 474 whose output is connected to thefirst input of the NAND gate 450.

Referring now again to the third multiplexor 430, the output of the NANDgate 450 is connected to the second data input of the third multiplexor430. The control input of the third multiplexor 430 is connected to amultiplier bit m[i+2] 403. The output of the third multiplexor 430 isconnected to the input lead of a fifth inverter 478. The output lead ofthe fifth inverter 478 contains the bit j of the i-th partial product490.

Referring now to FIG. 5, a truth table for the exemplary embodimentshown in FIG. 4 is displayed. By looking at the bits of the multiplier,one is able to determine the bit j of the i-th partial product partialthrough the utilization of the exemplary circuit of FIG. 4. The bit j ofthe i-th partial product may be the same as what would have beenproduced under the process known to the art, yet may be produced fasteras a result of the elimination of an additional step of recoding thebits of the multiplier.

An exemplary process of producing a final product is shown in FIG. 6.The number of multiplicand bits and multiplier bits may determine whichof the partial product generator cells of the present invention isutilized in order to produce the bit J of the i-th partial product. Theexemplary embodiment of the partial product generating cell of thepresent invention is not limited to a set of three bit multipliers and aset of two bit multiplicands as required for a radix 4 Booth encoder.The apparatus and method may be implemented with radices of greaterbases including but not limited to a radix 8 Booth encoder withoutdeparting from the scope and spirit of the present invention.

It is believed that the method and apparatus for alternate Booth partialproduct generation for a hardware multiplier of the present inventionand many of its attendant advantages will be understood by the forgoingdescription, and it will be apparent that various changes may be made inthe form, construction and arrangement of the components thereof withoutdeparting from the scope and spirit of the invention or withoutsacrificing all of its material advantages, the form herein beforedescribed being merely an explanatory embodiment thereof. It is theintention of the following claims to encompass and include such changes.

What is claimed is:
 1. A partial product generator cell suitable forhardware implementation of multipliers having three multiplier bits andtwo multiplicand bits, comprising: (a) a first multiplexor having twodata inputs, a control input, and an output, a first data input beingconnected to a first multiplier bit and said control input beingconnected to a second multiplier bit; (b) a second multiplexor havingtwo data inputs, a control input, and an output, said data inputs beingconnected to a first multiplicand bit and a second multiplicand bit; (c)a third multiplexor having two data inputs, a control input, and anoutput, said control input being connected to a third multiplier bit;(d) a AND gate having two input leads and an output lead, wherein afirst input lead is connected to said first multiplier bit and a secondinput lead is connected to said second multiplier bit; (e) a NAND gatehaving two input leads and an output lead, said output lead beingconnected to a first data input of said third multiplexor; (f) a twoinput two stack AOI gate having a first, second, third, and fourth inputleads, and an output lead, said first input lead being connected to saidoutput lead of said AND gate, said second input lead being connected toa first multiplicand input bit, said fourth input lead being connectedto a second multiplicand bit, and said output lead being connected to asecond data input of said third multiplexor; (g) a first inverter havingan input lead connected to said first multiplier bit and an output leadconnected to a second data input of said first multiplexor; (h) a secondinverter having an input lead connected to said output of said firstmultiplexor and an output lead connected to said third input lead ofsaid two input two stack AOI gate; (i) a third inverter having an inputlead connected to said output lead of said AND gate and an output leadconnected to a first input lead of said NAND gate; (j) a fourth inverterhaving an input lead connected to said output of said second multiplexorand an output lead connected to a second input lead of said NAND gate;and (k) a fifth inverter having an input lead and an output lead,wherein said input lead is connected to said output of said thirdmultiplexor.
 2. The partial product generator cell as claimed in claim1, wherein a partial product is produced at said output lead of saidfifth inverter.
 3. The partial product generator cell as claimed inclaim 1, wherein the first, second and third multiplier bits aredirectly utilized to perform the selects of the first and secondmultiplicand to generate partial products.
 4. The partial productgenerator cell as claimed in claim 1, wherein said generator may beplaced within a single cell.